From 48ac9384af98fb942780aa33b51912e8ded49f74 Mon Sep 17 00:00:00 2001 From: Jean Pierre Cimalando Date: Sun, 27 Sep 2020 22:57:31 +0200 Subject: [PATCH 1/2] Update ScopedFTZ asm for arm64 --- src/sfizz/ScopedFTZ.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/sfizz/ScopedFTZ.cpp b/src/sfizz/ScopedFTZ.cpp index 1f5b1c58..22c2c1e4 100644 --- a/src/sfizz/ScopedFTZ.cpp +++ b/src/sfizz/ScopedFTZ.cpp @@ -19,10 +19,14 @@ ScopedFTZ::ScopedFTZ() unsigned mask = _MM_DENORMALS_ZERO_MASK | _MM_FLUSH_ZERO_MASK; registerState = _mm_getcsr(); _mm_setcsr((registerState & (~mask)) | mask); -#elif SFIZZ_HAVE_NEON +#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM intptr_t mask = (1 << 24); asm volatile("vmrs %0, fpscr" : "=r"(registerState)); - asm volatile("vmsr fpscr, %0" : : "ri"((registerState & (~mask)) | mask)); + asm volatile("vmsr fpscr, %0" : : "r"((registerState & (~mask)) | mask)); +#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64 + intptr_t mask = (1 << 24); + asm volatile("mrs %0, fpcr" : "=r"(registerState)); + asm volatile("msr fpcr, %0" : : "r"((registerState & (~mask)) | mask)); #endif } @@ -30,7 +34,9 @@ ScopedFTZ::~ScopedFTZ() { #if SFIZZ_HAVE_SSE _mm_setcsr(registerState); -#elif SFIZZ_HAVE_NEON - asm volatile("vmrs %0, fpscr" : : "ri"(registerState)); +#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM + asm volatile("vmrs %0, fpscr" : : "r"(registerState)); +#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64 + asm volatile("mrs %0, fpcr" : : "r"(registerState)); #endif } From 8ebd256290006dbe57bfe0fe93877c0b3051bd31 Mon Sep 17 00:00:00 2001 From: Jean Pierre Cimalando Date: Sun, 27 Sep 2020 23:07:55 +0200 Subject: [PATCH 2/2] FPCR register is 64-bit --- src/sfizz/ScopedFTZ.cpp | 8 ++++---- src/sfizz/ScopedFTZ.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/sfizz/ScopedFTZ.cpp b/src/sfizz/ScopedFTZ.cpp index 22c2c1e4..46ca9424 100644 --- a/src/sfizz/ScopedFTZ.cpp +++ b/src/sfizz/ScopedFTZ.cpp @@ -18,13 +18,13 @@ ScopedFTZ::ScopedFTZ() #if SFIZZ_HAVE_SSE unsigned mask = _MM_DENORMALS_ZERO_MASK | _MM_FLUSH_ZERO_MASK; registerState = _mm_getcsr(); - _mm_setcsr((registerState & (~mask)) | mask); + _mm_setcsr((static_cast(registerState) & (~mask)) | mask); #elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM - intptr_t mask = (1 << 24); + uintptr_t mask = 1u << 24; asm volatile("vmrs %0, fpscr" : "=r"(registerState)); asm volatile("vmsr fpscr, %0" : : "r"((registerState & (~mask)) | mask)); #elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64 - intptr_t mask = (1 << 24); + uintptr_t mask = 1u << 24; asm volatile("mrs %0, fpcr" : "=r"(registerState)); asm volatile("msr fpcr, %0" : : "r"((registerState & (~mask)) | mask)); #endif @@ -33,7 +33,7 @@ ScopedFTZ::ScopedFTZ() ScopedFTZ::~ScopedFTZ() { #if SFIZZ_HAVE_SSE - _mm_setcsr(registerState); + _mm_setcsr(static_cast(registerState)); #elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM asm volatile("vmrs %0, fpscr" : : "r"(registerState)); #elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64 diff --git a/src/sfizz/ScopedFTZ.h b/src/sfizz/ScopedFTZ.h index 6fea43b0..15f024d9 100644 --- a/src/sfizz/ScopedFTZ.h +++ b/src/sfizz/ScopedFTZ.h @@ -5,6 +5,7 @@ // If not, contact the sfizz maintainers at https://github.com/sfztools/sfizz #pragma once +#include /** * @brief Flush floating points to zero and disable denormals as an RAII helper. @@ -16,5 +17,5 @@ public: ScopedFTZ(); ~ScopedFTZ(); private: - unsigned registerState; + uintptr_t registerState; };