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FPCR register is 64-bit

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Jean Pierre Cimalando 2020-09-27 23:07:55 +02:00
parent 48ac9384af
commit 8ebd256290
2 changed files with 6 additions and 5 deletions
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8
src/sfizz/ScopedFTZ.cpp
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@ -18,13 +18,13 @@ ScopedFTZ::ScopedFTZ()
#if SFIZZ_HAVE_SSE
unsigned mask = _MM_DENORMALS_ZERO_MASK | _MM_FLUSH_ZERO_MASK;
registerState = _mm_getcsr();
_mm_setcsr((registerState & (~mask)) | mask);
_mm_setcsr((static_cast<unsigned>(registerState) & (~mask)) | mask);
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM
intptr_t mask = (1 << 24);
uintptr_t mask = 1u << 24;
asm volatile("vmrs %0, fpscr" : "=r"(registerState));
asm volatile("vmsr fpscr, %0" : : "r"((registerState & (~mask)) | mask));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64
intptr_t mask = (1 << 24);
uintptr_t mask = 1u << 24;
asm volatile("mrs %0, fpcr" : "=r"(registerState));
asm volatile("msr fpcr, %0" : : "r"((registerState & (~mask)) | mask));
#endif
@ -33,7 +33,7 @@ ScopedFTZ::ScopedFTZ()
ScopedFTZ::~ScopedFTZ()
{
#if SFIZZ_HAVE_SSE
_mm_setcsr(registerState);
_mm_setcsr(static_cast<unsigned>(registerState));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM
asm volatile("vmrs %0, fpscr" : : "r"(registerState));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64

3
src/sfizz/ScopedFTZ.h
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@ -5,6 +5,7 @@
// If not, contact the sfizz maintainers at https://github.com/sfztools/sfizz
#pragma once
#include <cstdint>
/**
* @brief Flush floating points to zero and disable denormals as an RAII helper.
@ -16,5 +17,5 @@ public:
ScopedFTZ();
~ScopedFTZ();
private:
unsigned registerState;
uintptr_t registerState;
};