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Merge pull request #455 from jpcima/ftz-asm

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Update FTZ assembly to support ARM64
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JP Cimalando 2020-09-27 23:40:36 +02:00 • committed by GitHub
commit 13a3c9fd61
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2 changed files with 15 additions and 8 deletions
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20
src/sfizz/ScopedFTZ.cpp
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@ -18,19 +18,25 @@ ScopedFTZ::ScopedFTZ()
#if SFIZZ_HAVE_SSE
unsigned mask = _MM_DENORMALS_ZERO_MASK | _MM_FLUSH_ZERO_MASK;
registerState = _mm_getcsr();
_mm_setcsr((registerState & (~mask)) | mask);
#elif SFIZZ_HAVE_NEON
intptr_t mask = (1 << 24);
_mm_setcsr((static_cast<unsigned>(registerState) & (~mask)) | mask);
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM
uintptr_t mask = 1u << 24;
asm volatile("vmrs %0, fpscr" : "=r"(registerState));
asm volatile("vmsr fpscr, %0" : : "ri"((registerState & (~mask)) | mask));
asm volatile("vmsr fpscr, %0" : : "r"((registerState & (~mask)) | mask));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64
uintptr_t mask = 1u << 24;
asm volatile("mrs %0, fpcr" : "=r"(registerState));
asm volatile("msr fpcr, %0" : : "r"((registerState & (~mask)) | mask));
#endif
}
ScopedFTZ::~ScopedFTZ()
{
#if SFIZZ_HAVE_SSE
_mm_setcsr(registerState);
#elif SFIZZ_HAVE_NEON
asm volatile("vmrs %0, fpscr" : : "ri"(registerState));
_mm_setcsr(static_cast<unsigned>(registerState));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_ARM
asm volatile("vmrs %0, fpscr" : : "r"(registerState));
#elif SFIZZ_HAVE_NEON && SFIZZ_CPU_FAMILY_AARCH64
asm volatile("mrs %0, fpcr" : : "r"(registerState));
#endif
}

3
src/sfizz/ScopedFTZ.h
View file

@ -5,6 +5,7 @@
// If not, contact the sfizz maintainers at https://github.com/sfztools/sfizz
#pragma once
#include <cstdint>
/**
* @brief Flush floating points to zero and disable denormals as an RAII helper.
@ -16,5 +17,5 @@ public:
ScopedFTZ();
~ScopedFTZ();
private:
unsigned registerState;
uintptr_t registerState;
};